As data-center infrastructure, AI computing, high-speed networking, and advanced communication systems continue to evolve, 112G SerDes has become an important technology for high-bandwidth interconnects. However, transmitting 112 Gb/s signals across a printed circuit board requires much more than conventional high-speed routing.

At 112G PAM4, the signal channel becomes highly sensitive to insertion loss, impedance discontinuities, crosstalk, via transitions, and manufacturing variation. PCB materials, stackup design, copper roughness, and fabrication tolerances can all influence the final signal-integrity performance.

This article explains the main 112G PCB signal integrity design considerations and discusses how early cooperation with an experienced PCB manufacturer can improve manufacturability and channel consistency.

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Why Is 112G PCB Signal Integrity So Challenging?

112G interfaces commonly use PAM4 signaling, which transmits two bits per symbol through four voltage levels. Compared with traditional NRZ signaling, PAM4 provides greater data throughput at a lower symbol rate, but its smaller voltage margins make the signal more sensitive to noise and distortion.

For a 112G PAM4 link:

• Data rate: 112 Gb/s per lane

• Symbol rate: approximately 56 GBd

• Nyquist frequency: approximately 28 GHz

The actual channel requirements depend on the SerDes device, link architecture, equalization capability, channel length, and applicable system specifications.

A complete 112G channel may include the package, PCB traces, vias, connectors, cables, and receiver. Therefore, the PCB cannot be evaluated in isolation. Its electrical performance must fit within the total channel budget.

Key 112G PCB Signal Integrity Design Considerations

1. Select Low-Loss Materials and Plan the Stackup Carefully

Material selection is one of the first decisions affecting 112G signal integrity. At high frequencies, dielectric loss and conductor loss can consume a significant portion of the channel budget.

When selecting materials, engineers should evaluate:

• Dielectric constant and its frequency  stability

• Dissipation factor

• Copper surface roughness

• Resin content and dielectric thickness

• Glass-weave effects

• Compatibility with the required  lamination process

• Availability and consistency during  volume production

A low-Dk material is not automatically the best choice. The design team should evaluate the complete material profile, including loss characteristics and impedance behavior. The stackup should also be designed around the high-speed channel requirements. The distance between signal layers and reference planes directly affects trace geometry, differential impedance, and crosstalk.

2. Control Differential Impedance

112G differential pairs require carefully controlled impedance throughout the entire signal path. Impedance discontinuities can cause reflections and reduce the available signal margin.

Differential impedance is affected by:

• Trace width and spacing

• Copper thickness

• Dielectric thickness

• Material dielectric constant

• Reference-plane configuration

• Etching variation

• Solder mask effects

• Via and connector geometry

The trace width and spacing should be calculated using the actual stackup rather than a generic design rule. The PCB manufacturer should review the stackup and confirm whether the required impedance can be manufactured consistently.

Impedance control should also cover transitions such as:

• BGA fan-out regions

• Via fields

• Connector launches

• Layer changes

• AC-coupling capacitor areas

• Trace-width transitions

3. Minimize Insertion Loss

At 112G, insertion loss is a major factor in channel performance. Loss is influenced by both the dielectric material and the copper conductors.

To reduce unnecessary loss, designers should consider:

• Using suitable low-loss or ultra-low-loss laminates

• Keeping high-speed routes as short as  practical

• Avoiding unnecessary layer changes

• Selecting copper foil with appropriate roughness characteristics

• Minimizing unnecessary connectors and  transitions

• Optimizing trace geometry for the  selected stackup

• Including package and connector losses  in the channel budget

The maximum acceptable trace length should not be defined by a universal rule. It depends on the material, stackup, copper profile, via structures, connector characteristics, transmitter and receiver performance, and equalization strategy.

4. Optimize Via Transitions and Reduce Via Stubs

Vias create three-dimensional discontinuities in high-speed channels. Their pads, barrels, anti-pads, and unused sections can introduce parasitic capacitance, inductance, and resonance.

For 112G designs, engineers may evaluate the use of:

• Back-drilled through-hole vias

• Blind and buried vias

• Microvias

• Via-in-pad structures

• Optimized anti-pad geometry

• Ground stitching vias

• Shorter layer-transition structures

Back drilling can remove most of the unused plated barrel from a through-hole via and reduce the electrical impact of a via stub. However, the back-drill diameter, depth, residual stub length, and clearance must be determined according to the actual stackup and signal-integrity analysis.

Back drilling should not be specified solely by using a general depth tolerance. The PCB manufacturer must confirm the achievable process capability for the specific board structure.

5. Manage Crosstalk and Return-Current Paths

At 112G, even relatively small amounts of unwanted coupling may affect the signal eye and bit-error performance.

Crosstalk can be controlled by:

• Increasing spacing between sensitive differential pairs

• Avoiding long parallel routing

• Separating high-speed signals from noisy  power circuits

• Maintaining a continuous reference plane

• Avoiding routing across plane splits or  voids

• Optimizing the arrangement of adjacent  signal layers

• Reviewing via-field coupling and connector-launch geometry

There is no universal trace-spacing value suitable for every 112G design. Spacing should be determined according to the stackup, trace geometry, aggressor-victim relationship, and simulation results.

A continuous reference plane is particularly important because it provides a predictable return-current path and helps reduce unwanted electromagnetic coupling.

6. Consider Glass-Weave Effects and Pair Skew

At very high data rates, the difference between the electrical properties of glass fibers and resin can affect the propagation delay of differential traces.

If the two traces of a differential pair encounter different glass-weave structures, they may experience different propagation delays. This can introduce intra-pair skew and common-mode conversion.

Depending on the design and material system, engineers may consider:

• Adjusting the routing angle

• Using suitable spread-glass materials

• Avoiding routing patterns that strongly  follow a single glass bundle

• Reviewing pair skew through simulation

• Coordinating material selection with the  PCB manufacturer

The actual impact depends on the laminate construction, trace geometry, routing direction, and channel requirements.

Manufacturing Factors That Affect 112G Signal Integrity

For 112G PCB projects, manufacturing consistency is as important as the original layout. Small variations in trace geometry, dielectric thickness, copper thickness, or layer registration may change the electrical behavior of the finished board.

Manufacturing Factor	Potential Impact on 112G Performance
Dielectric thickness variation	Changes differential impedance and propagation delay
Trace-width variation	Affects impedance and conductor loss
Copper roughness	Influences high-frequency conductor loss
Layer registration	Affects via alignment and high-density transitions
Via drilling accuracy	Influences via geometry and transition consistency
Lamination consistency	Affects stackup thickness and impedance repeatability
Back-drill depth and position	Influences residual stub length and via reliability
Material batch consistency	May affect dielectric and loss characteristics

 

The specific acceptance criteria should be agreed upon during engineering review. A general manufacturing tolerance should not be treated as a guaranteed 112G electrical performance specification.

How Can PCBBUY Support Complex High-Speed PCB Projects?

PCBBUY focuses on PCB applications in automotive electronics, industrial control, power and electrical systems, power supplies, energy storage, new energy, and embodied robotics. These applications may require a combination of high-density routing, complex multilayer structures, controlled impedance, and reliable manufacturing performance.

Relevant PCBBUY capabilities include:

• High-frequency and high-speed materials: Support for materials from Rogers, TUC, Isola, and other manufacturers

• Low-Dk and low-Df material applications: Suitable for projects requiring careful control of high-speed      transmission loss

• Mixed-material lamination: Support for asymmetric and heterogeneous mixed-material structures

• HDI manufacturing: Support for first-order and second-order HDI structures

• Laser-drilled blind vias: Minimum laser-drilled blind via diameter of Φ0.075 mm

• Mechanically drilled blind vias: Minimum mechanically drilled blind via diameter of Φ0.15 mm

• Large-size PCB production: Maximum production size of 1000 × 600 mm

• Quality inspection: AOI, flying-probe testing, and four-wire low-resistance testing

For 112G PCB projects, PCBBUY’s engineering team should review the complete design package, including the stackup, material requirements, impedance targets, high-speed routing constraints, via structures, and fabrication notes.

The published manufacturing capabilities should be evaluated according to the specific project requirements. For example, HDI and controlled-depth drilling capabilities can support complex interconnection structures, but they do not by themselves establish 112G channel compliance.

What Should Be Confirmed Before 112G PCB Production?

Before releasing a 112G PCB design for fabrication, the designer and manufacturer should review:

1. The complete stackup and selected high-speed materials

2. Differential impedance targets and test requirements

3. Trace width, spacing, and copper thickness

4. Insertion-loss and return-loss targets

5. Via structures, anti-pad geometry, and back-drilling requirements

6. Reference-plane continuity

7. Crosstalk and pair-skew constraints

8. Connector and BGA launch structures

9. Manufacturing tolerances and  registration limits

10. Signal-integrity simulation and  validation requirements

Early engineering communication helps identify conflicts between electrical performance, routing density, material availability, and manufacturing feasibility.

Conclusion

The most important 112G PCB signal integrity design considerations include low-loss material selection, stackup optimization, impedance control, insertion-loss management, via-transition design, crosstalk reduction, and manufacturing consistency.

At 112G PAM4, the PCB must be treated as an engineered transmission-line system rather than a simple electrical connection. Traces, vias, reference planes, connectors, and materials all contribute to the final channel performance.

For complex applications such as automotive electronics, industrial control, power systems, energy storage, new-energy equipment, and embodied robotics, early cooperation between the design team and PCB manufacturer can help establish a manufacturable and repeatable high-speed interconnect structure.

FAQ

1. What are the main 112G PCB signal integrity design considerations?

The main considerations include low-loss materials, stackup design, controlled differential impedance, insertion-loss management, via optimization, crosstalk control, reference-plane continuity, and manufacturing consistency.

2. Does 112G always mean 112 GBd?

No. In a typical 112G PAM4 application, the data rate is approximately 112 Gb/s per lane, while the symbol rate is approximately 56 GBd because PAM4 carries two bits per symbol. The exact signaling format depends on the application.

3. What is the approximate Nyquist frequency of a 112G PAM4 signal?

For a 112G PAM4 signal operating at approximately 56 GBd, the Nyquist frequency is approximately 28 GHz. The actual design bandwidth and channel requirements depend on the interface implementation and system architecture.

4. Are standard FR-4 materials suitable for 112G PCB designs?

Material suitability depends on the channel length, loss budget, stackup, copper roughness, equalization capability, and complete system requirements. Standard FR-4 should not be selected without evaluating its high-frequency loss characteristics.

5. Is back drilling necessary for every 112G PCB?

No. Back drilling may be useful when through-hole via stubs create unacceptable discontinuities, but its necessity depends on the via structure, channel design, stackup, and signal-integrity analysis.

6. Is there a universal trace-spacing rule for 112G differential pairs?

No. The appropriate spacing depends on trace geometry, dielectric thickness, material properties, adjacent routing, and crosstalk requirements. Field-solver analysis and channel simulation are more reliable than applying a universal spacing rule.

7. Can PCBBUY manufacture PCBs for 112G applications?

PCBBUY supports high-frequency materials, mixed-material lamination, HDI structures, and other manufacturing processes relevant to complex high-speed PCB projects. However, 112G performance must be evaluated based on the complete channel design, manufacturing requirements, and applicable validation procedures.

8. What files should be provided when requesting a quotation for a 112G PCB?

The design package should include the fabrication data, complete stackup, material requirements, impedance targets, drill files, high-speed routing specifications, via and back-drilling details if applicable, and inspection requirements.