As high-performance computing, artificial intelligence, and advanced industrial systems demand greater bandwidth, PCI Express 6.0 introduces more stringent requirements for PCB design and signal integrity. Operating at 64.0 GT/s, PCIe 6.0 uses PAM4 signaling, together with Forward Error Correction (FEC) and Flit-based encoding, to increase data throughput.

Compared with previous PCIe generations, PCIe 6.0 is more sensitive to noise, loss, crosstalk, impedance discontinuities, and manufacturing variation. Therefore, designers must consider the complete high-speed channel, including the PCB material, stackup, vias, connectors, and routing geometry.

This article explains key PCB design rules for PCI Express 6.0 and outlines how a capable PCB manufacturer can support demanding high-speed applications.

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Why Is PCIe 6.0 PCB Design More Challenging?

PCIe 6.0 doubles the raw transfer rate of PCIe 5.0 to 64.0 GT/s and uses four-level pulse-amplitude modulation instead of conventional NRZ signaling. PAM4 transmits two bits per symbol but provides smaller voltage margins between signal levels, making the channel more sensitive to noise and distortion.

As a result, a PCIe 6.0 PCB must provide:

• Controlled differential impedance

• Low insertion loss

• Low return loss

• Minimal crosstalk

• Stable reference planes

• Carefully designed vias and transitions

• Consistent material and manufacturing  performance

It is important to understand that PCB layout alone cannot guarantee PCIe 6.0 compliance. Compliance depends on the complete channel and the applicable PCI-SIG requirements, including the package, connector, PCB, and other interconnect components.

Key PCB Design Rules for PCI Express 6.0

1. Use a Suitable High-Speed PCB Material

Material selection is one of the most important factors in PCIe 6.0 design. Designers should evaluate dielectric constant, dissipation factor, copper roughness, resin content, and frequency-dependent insertion loss.

Low-loss materials can help reduce transmission loss, but the material should be selected according to the complete channel budget rather than by choosing a low-Dk value alone.

For complex high-speed boards, the material datasheet should be reviewed together with the actual stackup and signal-integrity simulation results.

2. Control Differential Impedance

PCIe differential pairs should be routed according to the impedance target defined by the design and applicable interface requirements.

The following factors affect differential impedance:

• Trace width and spacing

• Copper thickness

• Dielectric thickness

• Dielectric constant

• Reference-plane configuration

• Solder mask effects

• Etching variation

The impedance target should be calculated using the actual stackup rather than relying on generic trace-width rules. The PCB manufacturer should review the proposed stackup before fabrication and confirm whether the specified impedance can be achieved with the selected materials and copper thicknesses.

3. Keep Differential Pairs Short and Consistent

PCIe 6.0 routing should minimize unnecessary channel length and avoid sharp changes in geometry.

Practical layout recommendations include:

• Keep each differential pair together  throughout the route.

• Maintain consistent trace width and spacing.

• Avoid unnecessary layer changes.

• Minimize vias and connectors in the signal path.

• Avoid abrupt trace-width changes.

• Match the electrical length of the positive and negative traces.

• Keep the pair away from noisy power circuits and unrelated high-speed signals.

Length matching should be based on the actual timing and channel requirements. Excessive serpentine routing can introduce additional discontinuities and coupling, so designers should avoid adding unnecessary meanders.

4. Optimize Via Transitions and Reduce Via Stubs

Vias can create impedance discontinuities and unwanted resonances in high-speed channels. Long unused portions of through-hole vias can act as via stubs and degrade signal integrity.

For PCIe 6.0 designs, designers may consider:

• Back drilling

• Blind vias

• Buried vias

• Microvias

• Optimized layer transitions

• Via-in-pad structures where appropriate

Back drilling can remove most of the unused plated barrel from a through-hole via. However, the required back-drill depth, residual stub length, and clearance must be determined from the stackup and signal-integrity analysis.

The back-drilling process should be reviewed with the PCB manufacturer in advance. Designers should not assume that a general controlled-depth drilling tolerance automatically applies to every back-drilling application.

5. Maintain a Continuous Reference Plane

High-speed differential pairs should be routed over a continuous reference plane whenever possible. A signal crossing a split or gap in its reference plane may experience a discontinuity in its return-current path.

Designers should:

• Avoid routing across plane splits.

• Provide a stable reference plane along the complete route.

• Minimize gaps around high-speed transitions.

• Check reference-plane continuity near connectors and vias.

• Use appropriate stitching structures where required by the design.

Power distribution and high-speed signal routing should also be planned together to reduce noise coupling and maintain a stable electrical environment.

6. Control Crosstalk and Unwanted Coupling

Because PCIe 6.0 uses PAM4 signaling with reduced voltage separation between levels, unwanted noise and crosstalk require careful consideration.

Crosstalk can be reduced by:

• Increasing spacing between unrelated high-speed routes

• Avoiding long parallel traces

• Using appropriate reference-plane structures

• Separating sensitive signal groups from noisy power circuitry

• Limiting unnecessary routing density

• Reviewing connector and via-field geometry

The exact spacing requirement depends on the stackup, trace geometry, signal environment, and simulation results. A universal “3W” rule should not be treated as a substitute for actual high-speed channel analysis.

Important Manufacturing Parameters for PCIe 6.0 PCBs

The following parameters should be reviewed during the engineering stage. These are design considerations rather than universal PCIe 6.0 compliance limits.

PCB Parameter	Why It Matters for PCIe 6.0
Dielectric material and loss characteristics	Affect insertion loss and signal attenuation
Trace width and spacing	Influence differential impedance and coupling
Copper roughness	Can contribute to conductor loss at high frequencies
Layer-to-layer registration	Affects via alignment and high-density routing reliability
Via structure	Influences discontinuity, stub length, and transition performance
Stackup consistency	Helps maintain predictable impedance and electrical length
Reference-plane continuity	Supports a stable return-current path
Manufacturing tolerance	Can affect impedance, registration, and channel repeatability

 

How Can PCBBUY Support Complex High-Speed PCB Projects?

PCBBUY serves applications including automotive electronics, industrial control, power and electrical systems, power supplies, energy storage, new energy, and embodied robotics. 

These fields may involve high-speed communication, compact multilayer structures, high power density, and demanding reliability requirements.

Relevant PCBBUY PCB manufacturing capabilities include:

• High-frequency and high-speed materials: Support for materials from Rogers, TUC, Isola, and other manufacturers

• Low-loss material processing: Support for low-Dk and low-Df material applications

• Mixed-material lamination: Support for asymmetric and heterogeneous mixed-material lamination

• HDI manufacturing: Support for first-order and second-order HDI structures

• Laser-drilled blind vias: Minimum laser-drilled blind via diameter of Φ0.075 mm

• Mechanically drilled blind vias: Minimum mechanically drilled blind via diameter of Φ0.15 mm

• Large-size PCB production: Maximum production size of 1000 × 600 mm

• Quality inspection: AOI, flying-probe testing, and four-wire low-resistance testing

For PCIe 6.0-related projects, PCBBUY’s engineering team should review the complete stackup, impedance requirements, material selection, routing constraints, via structures, and fabrication notes before production.

These manufacturing capabilities can support complex high-speed PCB development, but PCIe 6.0 compliance must be verified through complete system-level design and the applicable compliance testing process.

What Should Be Confirmed Before PCB Production?

Before releasing a PCIe 6.0 PCB design for manufacturing, the designer and manufacturer should review:

1. The complete layer stackup and material selection

2. Differential impedance requirements

3. Trace width, spacing, and copper thickness

4. High-speed via structures and back-drilling requirements

5. Reference-plane continuity

6. Back-drill diameter, depth, and residual stub requirements

7. Manufacturing tolerances and registration limits

8. Impedance-control and inspection requirements

9. Signal-integrity simulation results

10. The applicable PCIe compliance and validation plan

Early engineering communication can help identify potential conflicts between electrical requirements, routing density, manufacturing tolerances, and production cost.

Conclusion

The key PCB design rules for PCI Express 6.0 focus on controlling loss, impedance, crosstalk, via discontinuities, and manufacturing variation. Because PCIe 6.0 uses 64.0 GT/s PAM4 signaling, the available signal margin is more sensitive to channel imperfections than in earlier generations.

A successful design requires more than short traces or strict length matching. Material selection, stackup planning, reference-plane continuity, via optimization, impedance control, and complete channel simulation must be considered together.

For automotive electronics, industrial control, power systems, energy storage, new-energy equipment, and embodied robotics, early cooperation between the PCB designer and manufacturer can improve manufacturability and help establish a more predictable high-speed interconnection structure.

FAQ

1. What are the most important PCB design rules for PCI Express 6.0?

The most important considerations include controlled differential impedance, low-loss materials, short and consistent signal paths, optimized vias, continuous reference planes, crosstalk control, and strict stackup management.

2. What signaling technology does PCIe 6.0 use?

PCIe 6.0 uses four-level pulse-amplitude modulation, or PAM4, and supports a raw transfer rate of 64.0 GT/s. It also introduces Flit-based encoding and Forward Error Correction.

3. Does PCIe 6.0 always require low-loss PCB materials?

Not every design uses the same material specification. However, material loss should be evaluated carefully because it directly affects the insertion loss and available channel margin. The final material choice should be based on channel analysis and the complete system design.

4. Should PCIe 6.0 PCBs use back drilling?

Back drilling may be beneficial when long through-hole via stubs create unacceptable signal-integrity problems. Its necessity depends on the via structure, channel design, stackup, and simulation results.

5. Is there a universal trace width for PCIe 6.0 differential pairs?

No. Trace width and spacing depend on the dielectric thickness, copper thickness, material properties, stackup, and required impedance. The correct geometry should be calculated from the actual PCB stackup.

6. Can HDI technology be used in PCIe 6.0 PCB designs?

Yes. HDI structures, blind vias, and microvias may help reduce via length and improve routing density. However, the selected structure must be evaluated for electrical performance, reliability, and manufacturing feasibility.

7. Can PCBBUY guarantee PCIe 6.0 compliance based on its PCB manufacturing capabilities?

Manufacturing capabilities alone do not establish PCIe 6.0 compliance. PCBBUY can review high-speed PCB requirements and support relevant material, stackup, HDI, and manufacturing processes, while complete compliance depends on the entire channel and the applicable validation procedures.

8. What should be provided when requesting a quotation for a PCIe 6.0 PCB?

The design package should include the Gerber or other fabrication data, layer stackup, material requirements, impedance targets, drill files, high-speed routing notes, back-drilling details if applicable, and relevant inspection requirements.