What Is IC Packaging Substrate Technology in PCB？
Integrated Circuit (IC) packaging progresses along with the development of integrated circuits. With the continuous development of various industries such as aerospace, aviation, machinery, light industry, and chemical industry, the entire machine also changes towards multi-function and miniaturization. Thus, it requires that the integration degree of IC becomes higher and higher, the functions become more and more complex. Correspondingly, it requires that the packaging density of integrated circuits becomes larger and larger, the number of leads becomes more and more, while the volume becomes smaller and smaller, the quality becomes lighter and lighter, and the upgrading becomes faster and faster. The rationality and scientificity of the packaging structure will directly affect the quality of integrated circuits.
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Overview of IC Packaging Substrates
Packaging Overview
Traditional IC packaging uses lead frames as the conducting lines of IC and the carrier for supporting IC, which connects the pins on both sides or around the lead frame. With the development of IC packaging technology and the increase in the number of pins (more than 300 pins), the traditional QFP (Quad Flat Package) packaging form has restricted its development. Thus, in the mid-1990s, a new type of IC packaging form represented by BGA (Ball Grid Array) and CSP (Chip Scale Package) came out, and subsequently a necessary new carrier for semiconductor chip packaging was produced, which is the IC packaging substrate. Currently, the mainstream products of IC substrates according to their packaging methods include three types of substrates: BGA, CSP and FC (Flip Chip), with the latter two being the mainstream.
The main functions of packaging: ① Isolate the exposed chip from the air to prevent the circuits on the chip from being corroded; ② Provide physical and mechanical support to prevent damage to the chip from external forces; ③ Between the highly refined chip and the less refined printed circuit board, a more refined packaging substrate is needed as an intermediate bridge for transmitting information.
Packaging can generally be divided into five packaging levels.
(1) Level 0 packaging: Refers to chips or wafers/dies that have not been packaged. (2) Level 1 packaging: Refers to the packaging of the substrate and the chip.
(3) Level 2 packaging: Refers to the packaging structure of level 1 packaged onto the printed circuit board.
(4) Level 3 packaging: Refers to the assembled system level.
(5) Level 4 packaging: Refers to the connection between systems, such as the connection between computers.
IC Packaging Technology
Since around the 1970s, electronic packaging has emerged from nothing, from transistor packaging to chip component packaging, from insert packaging to surface mount packaging, from metal packaging, ceramic packaging, metal-ceramic packaging to plastic packaging. Plastic packaging has a low cost, simple process, and is suitable for mass production. Therefore, it has strong vitality. Since its birth, it has developed faster and faster and occupied an increasing share in packaging.
The manufacturing process of IC packaging technology can be divided into two major parts: The processes before plastic packaging are called the front-end processes, and the processes after forming are called the back-end processes.
1. Silicon Wafer Thinning
The thickness of the chip brings certain difficulties to the division of the chip. Therefore, after the fabrication of the chip's circuit layer is completed, the backside of the silicon wafer needs to be thinned to the required thickness. A film (blue film) with a metal ring or plastic frame is attached to the backside of the chip to protect the chip's circuit before subsequent cutting.
The backside thinning technologies of silicon wafers mainly include grinding, lapping, chemical polishing, dry polishing, electrochemical corrosion, wet corrosion, plasma enhanced chemical corrosion, atmospheric pressure plasma corrosion, etc.
2. Chip Cutting
The process of separating each chip through wafer cutting is called chip cutting. The equipment used is called a cutting machine, also known as a dicing machine.
Nowadays, cutting machines are all automatic, and the blades are generally pulsed lasers or diamond. Cutting is divided into partial cutting (not cutting all the way through, leaving a residual thickness) and complete cutting. Complete cutting generally has neat cutting edges and few cracks; for partial cutting, a thimble is used to apply force to completely separate the chips, so there will be more or less a small number of micro-cracks and grooves at the ports.
Usually, the thinning process and chip cutting are usually combined to form two techniques: First, dicing before grinding (DBG). Before backside grinding, a certain depth of incision is made on the front side of the silicon wafer, and then grinding is performed. Second, dicing by thinning (DBT). Before thinning, a certain depth of incision is made by mechanical or chemical methods first, and then the grinding method is used to thin to a certain thickness. Finally, the remaining processing amount is removed by atmospheric pressure plasma corrosion technology. Both techniques can avoid or reduce the wafer warping caused by thinning and the edge damage caused by dicing, increasing the chip's anti-fragmentation ability. DBT can also remove the backside grinding damage of the silicon wafer and remove the micro-cracks and grooves caused by the chip.
3. Chip Mounting
Chip mounting, also known as chip bonding, is the process of fixing the chip on the packaging substrate or the pin frame carrier. The equipment for chip mounting is called a mounter. The main methods of chip mounting can be divided into four methods: eutectic bonding method, soldering bonding method, conductive adhesive bonding method and glass adhesive bonding method.
1) Eutectic Bonding Method
Eutectic reaction refers to the reaction in which a liquid of a certain composition simultaneously crystallizes two solid phases of a certain composition at a certain temperature. The point at which the reaction begins is called the eutectic point. The two solid phases generated are mechanically mixed together to form a basic structure with a fixed chemical composition, and are collectively referred to as eutectics.
Place the chip on the chip carrier of the ceramic substrate that has been plated with a gold film. Under a certain pressure (friction or ultrasound), with nitrogen as the protective gas, heat it to the eutectic point temperature. When the temperature is higher than the eutectic temperature, the gold-silicon alloy turns into a liquid Au-Si eutectic melt. After cooling, when the eutectic melt changes from the liquid phase to a mechanical mixture in the form of grains combined with each other - the gold-silicon eutectic melt and solidifies completely, a firm ohmic contact is thus formed, that is, eutectic bonding.
2) Soldering Bonding Method
Soldering bonding method is a process method for chip bonding using alloy reactions. Its process flow is to deposit a certain thickness of gold or nickel on the backside of the chip in a hot nitrogen atmosphere, deposit a metal layer of gold-palladium-silver or copper on the pad of the solder pad, and solder the chip on the pad with a lead-tin alloy solder. The alloy solder can be divided into hard solder and soft solder.
3) Conductive Adhesive Bonding Method
Conductive adhesive is an adhesive that has certain conductive properties after curing or drying. It usually consists mainly of matrix resin (such as epoxy resin) and conductive filler, that is, conductive particles (such as silver powder). The conductive particles are combined together through the bonding effect of the matrix resin to achieve the conductive connection of the material. The conductive particles play a conductive role, while the matrix resin plays a bonding role. The thermal expansion coefficient of the polymer resin is similar to that of the copper pins. The conductive adhesive method is a commonly used chip bonding method in packaging. Conductive adhesives are divided into paste conductive adhesives and solid films.
Paste conductive adhesive: Place the chip precisely on the chip pad where the conductive adhesive (binder) is applied to the appropriate thickness and contour with a syringe or injector for curing. Solid film: Cut it to the appropriate size and place it between the chip and the base pillar, and then perform thermocompression bonding. The use of solid film conductive adhesive can enable automated large-scale production.
4) Glass Adhesive Bonding Method
Glass adhesive is similar to conductive adhesive. It is made by mixing conductive metal powder, low-temperature glass powder and organic solvent into a paste. When using glass adhesive bonding, the glass adhesive is applied to the chip seat of the substrate by stamping, screen printing, dispensing and other methods, the chip is placed on the glass adhesive, and the substrate is heated to above the glass melting temperature to complete the bonding. Because the temperature for completing the bonding is higher than that of the conductive adhesive, it is only applicable to ceramic packaging.
4. Chip Interconnection
Chip interconnection is to connect the chip's bonding area with the I/O leads of the electronic packaging shell or the metal bonding area on the substrate. Common chip interconnection methods include wire bonding (WB), flip chip bonding (FCB) and tape automated bonding (TAB).
The limitations of the three connection technologies for different packaging forms and the integration degree of integrated circuit chips have different application scopes: Wire bonding is suitable for 3 to 257 leads; Tape automated bonding is suitable for 12 to 600 pins; Flip chip bonding is suitable for 6 to 16,000 pins. Therefore, flip chip bonding is suitable for high-density assembly.
1) Wire Bonding Process Technology
Wire Bonding (WB) process technology is a process technology that uses high-purity metal wires to bond the internal circuit of the chip before packaging and the I/O leads of the microelectronic packaging or the metal wiring bonding area (pad) on the substrate. Ensuring the external electrical interconnection of the chip and the packaging substrate, and the smooth input/output is an important step in the packaging process. Wire bonding technology can be divided into ultrasonic bonding, thermocompression bonding and thermosonic bonding.
The connecting wires include: gold wire, aluminum wire and copper wire. Among them, gold wire has the advantages of good corrosion resistance, strong toughness, high electrical conductivity and good thermal conductivity, so it is widely used; Aluminum wire is not suitable for forming solder balls due to easy oxidation when heated, and its toughness and heat resistance are not as good as gold wire. At the same time, the elongation fluctuation of aluminum wire is large, and the performance of the same batch of products varies greatly; Copper wire has low cost, high strength, good electrical conductivity and strong thermal conductivity, but its corrosion resistance is weak, and the pressure required for bonding is large, which is easy to damage the chip. To sum up, gold wire is currently the most ideal bonding wire. After the chip is connected to the packaging substrate through the bonding lead, and then precisely covered with a special protective organic material to isolate it from the outside, it has high stability and oxidation and corrosion resistance.
At present, the evaluation of whether WB is good mainly through tensile test and ductility test. Taking gold wire as an example, a fixed-length gold wire is selected, both ends are fixed, and it is pulled at a stable speed to read the extended length when it is pulled off and the force applied when it is pulled off.
The WB process is simple and low-cost, and is currently the most widely used packaging form.
2) Tape Automated Bonding Technology
Tape, that is, a ribbon carrier, refers to a lead frame formed by etching the copper foil on the ribbon-shaped insulating film. Tapes are generally made of PI and are provided with feed holes unified with the specifications of film at both sides. Tape automated bonding technology refers to a process technology that uses the metal foil wire of the spider-shaped lead image to interconnect the chip bonding area with the I/O of the electronic packaging shell or the metal wiring bonding area on the substrate. Its manufacturing process: First, complete the conductor pattern of the component pins on the polymer, then place the wafer on it corresponding to its bonding area, and finally perform batch bonding of all leads through the hot electrode at one time. As shown in Figure 7-5 is the physical picture of the TAB substrate.
The key technology of TAB is the chip bump technology. The surface of the IC chip is plated with a passivation protection layer, which is thicker than the electroplated bonding point. Therefore, it is necessary to first grow a bonding bump at the bonding point of the chip or the front end of the inner lead of the TAB tape before subsequent bonding. Generally, TAB tape technology is divided into bumped tape and bumped chip.
Advantages of TAB technology compared with WB technology:
(1) The bonding plane of TAB leads is low, and its structure is light, thin, short, small, and the height is < 1mm.
(2) The electrode size of TAB, and the distance between the electrodes and the bonding area are smaller than those of WB.
(3) Correspondingly, more I/O pins can be accommodated, and the installation density is higher.
(4) The R, C and L of the leads of TAB are smaller than those of WB, the speed is faster, and the high-frequency characteristics are better.
(5) TAB interconnection can be used for electrical aging, screening and testing of IC chips.
(6) TAB uses Cu foil leads, which have good heat and electricity conductivity and high mechanical strength.
(7) The bonding pull force of TAB solder joints is 3 to 10 times higher than that of WB.
(8) The size of the tape can be standardized and automated, which can be produced on a large scale to improve efficiency and reduce costs.
3) Flip Chip Process Technology
Flip Chip (FC) refers to interconnecting components directly to the substrate through solder balls on the chip with the component facing upwards, and it can also be called DCA (Direct Chip Attach). The main methods for making its bumps include evaporation/sputtering bump fabrication method, electroplating bump fabrication method, ball placement and template printing solder bump fabrication method.
Flip chip (abbreviated as FC) refers to directly interconnecting the component upward to the substrate through solder balls on the chip, and it can also be called DCA (direct chip attach). The main methods for fabricating its bumps include evaporation/sputtering bump fabrication method, electroplating bump fabrication method, ball placement and stencil printing for solder bump fabrication method.
The chip in WB packaging is facing upward, while the chip in FC packaging is facing downward. The solder areas on the chip are directly interconnected with the solder areas on the substrate. Therefore, the interconnects in FC technology are very short; the stray capacitance, interconnect resistance, and interconnect inductance generated are much smaller than those in WB, making it more suitable for high-frequency and high-speed electronic products; chip installation and interconnection can be carried out simultaneously, with a simple and fast process; in FC packaging, the area occupied by the chip is small, so the installation density of the chip increases, greatly increasing the number of I/Os, and the integration and interconnection are greatly improved. However, the FC packaging installation and interconnection process is difficult, the chip is facing downward, and solder joint inspection is difficult; the bump process is complex and costly; at the same time, its heat dissipation effect is low and needs to be improved.
5. Molding Technology
The technology of packaging the chip and lead frame after the chip interconnection is completed is called molding technology. Molding technologies include metal packaging, plastic packaging, ceramic packaging, etc. However, considering the cost and other aspects, plastic packaging is the most common packaging method, occupying about 90% of the market.
The molding technologies of plastic packaging include transfer molding, inject molding, pre-molding, etc. Currently, transfer molding technology is mainly used. The materials used in transfer molding technology are generally thermosetting polymers. The thermosetting plastic molding process is a combination of "hot runner injection molding" and "pressure molding". In the traditional hot runner injection molding, a certain temperature is maintained in the melt cavity. Under the action of external pressure, the clinker undergoes chip molding and obtains a certain chip shape in the mold cavity.
6. Deburring and Flash Removal
The phenomenon of flash and burr refers to the overflow of plastic resin, tape burrs, lead burrs, etc. in plastic packaging. The main process flow for deburring is: medium deburring and flash removal → solvent deburring and flash removal → water deburring and flash removal.
Medium deburring and flash removal: Flushing the module with abrasive materials (such as granular plastic balls) together with high-pressure air. During this process, the medium will slightly abrade the surface of the frame pins, which is helpful for the adhesion of solder and the metal frame.
Solvent deburring and flash removal: Usually only suitable for very thin burrs. Solvents include N-methylpyrrolidone (NMP) or dimethylfuran (NMF).
Water deburring and flash removal: It is to impact the module with high-pressure water flow. Sometimes abrasive materials are used together with high-pressure water flow.
7. Trim and Form
The trim and form process refers to cutting the dams between the leads outside the frame and the connected areas on the frame tape, and bending the leads into a certain shape to meet the assembly requirements. The trim and form process is divided into two procedures and can be completed mechanically at the same time. First, the trimming is done, then the solder is applied, and then the forming process is carried out. The advantage is that the cross-sectional area without solder application, such as the area of the incision, can be reduced.
8. Marking
Marking is the printing of indelible and clear marks on the top surface of the packaged module, including the manufacturer's information, country, period code, etc. The two most commonly used marking methods are ink marking and laser marking.
Ink marking: Using rubber to engrave the marking. Ink is a polymer compound and requires thermal curing or UV curing. Ink marking has higher requirements on the surface. If the surface is contaminated, the ink cannot be applied.
Laser marking: Using a laser to write marks on the module surface. The biggest advantage of laser marking is that the marking is not easy to erase and the process is simple; the disadvantage is that the handwriting is relatively light.
9. Solder Application
Solder application on the external leads of the frame after packaging is to apply a protective layer on the frame pins and increase their solderability. Currently, there are mainly two methods for solder application: electroplating and dip soldering.
Electroplating process flow:
Cleaning → Electroplating in the electroplating tank → Rinsing → Blowing dry → Drying (in the oven). Dip soldering process flow:
Deburring → Degreasing → Removing oxides → Dipping flux → Hot dip soldering → Cleaning → Drying.
Dip soldering is prone to uneven coating, thick in the middle and thin on the edges (caused by surface tension), while electroplating is thin in the middle and thick especially at the corners (caused by charge accumulation effect). Electroplating solution can also cause particle contamination.
A New Packaging Technology - Embedded Chip Technology
Embedded chip technology refers to a process technology that embeds the chip into the packaging substrate and then performs pattern electroplating to interconnect the chip and the substrate lines. Embedded technology is classified according to different pad connection methods and via connection methods.
1. Advantages of Embedded Chip Technology
1) Enabling higher density or miniaturization of the system
Conventional chips are mounted on the surface of the packaging substrate, and all signal connections are designed and arranged on the PCB surface pads. The system packaging formed by embedding the chips inside the packaging substrate will significantly shorten and reduce the connection points, wires, pads, and vias, thus having greater integration, flexibility, and adaptability.
2) Improving the reliability of system functions
Embedding the chips inside the packaging substrate and isolating them from the "atmosphere" environment enables these chips to receive the most effective protection; at the same time, due to the position of these chips embedded inside the printed circuit board and having the shortest wire (or via) connection, the failure rate of "connections" is eliminated and reduced.
3) Improving the performance of signal transmission
Since the chips are isolated from the atmosphere and receive the best protection, the signal transmission is more stable; the shortening or reduction of connection wires, pads, and vias ensures the integrity of signal transmission.
4) Entering the market faster and reducing production costs
Chip and substrate production occurs simultaneously at the same location, reducing transportation, storage, and management processes, as well as reducing "repeated" inspection and review steps. The shortened production cycle enables faster market entry and lower costs, enhancing the competitiveness of the product in the market.
2. Disadvantages of Embedding Active Components Between Substrates
The disadvantages of embedding active components between substrates are as follows:
(1) The manufacturing process of the packaging substrate, which is the traditional packaging carrier, needs to undergo significant changes, so many existing packaging substrate manufacturers have difficulty adapting to this transformation.
(2) For printed circuit board factories, due to production efficiency and economic benefits constraints, they cannot guarantee that the products embedding active components are completely qualified. In this regard, the top priority is to establish a set of design, inspection and measurement methods and standards.
(3) There are many issues that need to be addressed in the industrial structure, such as the need to establish a system for supplying chips from multiple manufacturers, etc.
3. Types of Embedded Chip Technology
Embedded chip technology can be divided into: embedding the chip first and then fabricating the substrate, embedding the chip halfway, and embedding the chip at the end. Figure 7-1l shows the schematic diagram of the embedded chip structure. First, the chip is attached to the semi-finished substrate, then resin is poured between the chip and the substrate through lamination, and the chip line and the substrate line are conducted through pattern electroplating. Finally, the substrate line is continued to be fabricated. This technology can greatly reduce the total thickness of the packaging substrate and the chip, and has better reliability. The technology of embedding the chip requires very mature packaging substrate fabrication technology. Once there is scrap, the chip will also be scrapped simultaneously.
PCB Knowledge ⋅ 12/30/2024 16:21
